Patent · US Active

Read assist circuitry for memory applications

US11475944B2 · kind B2 · utility

0Cited by

0References

19Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Rahul Mathur · Austin, US
Vivek Asthana · Greater Noida, IN
Ankur Goel · Bengaluru, IN
Nikhil Kaushik · Noida, IN
Rachit Ahuja · Noida, IN
Bikas Maiti · Austin, US
Yew Keong Chong · Austin, US

Key dates

Filing date	Nov 30, 2020
Grant date	Oct 18, 2022
Priority date	—
Expiry date	Nov 30, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/418
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.