Method of forming multi-threshold voltage devices and devices so formed
US11476121B2 · kind B2 · utility
1Cited by
9References
17Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 26, 2019 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Nov 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.