Semiconductor package and manufacturing method thereof
US11476211B2 · kind B2 · utility
0Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2020 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Dec 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device; and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.