Method used in forming an array of vertical transistors and method used in forming an array of memory cells individually comprising a vertical transistor and a storage device above the vertical transistor

US11476255B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventor

• Guangjun Yang · Shanghai, CN

Key dates

• Filing date: Sep 10, 2020
• Grant date: Oct 18, 2022
• Expiry date: Apr 14, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/488

Abstract

A method used in forming an array of vertical transistors comprises forming pillars individually comprising an upper source/drain region, a channel region vertically below the upper source/drain region, and sacrificial material above the upper source/drain region. Intervening material is about the sacrificial material of individual of the pillars. The intervening material and the sacrificial material comprise different compositions relative one another. Horizontally-elongated and spaced conductive gate lines are formed individually operatively aside the channel region of the individual pillars. The sacrificial material is removed to expose the upper source/drain region of the individual pillars and thereby form an opening in the intervening material directly above the upper source/drain region of the individual pillars. Metal material is formed in individual of the openings directly against the upper source/drain region of the individual pillars and atop the intervening material laterally outside of the openings. The metal material that is atop the intervening material interconnects the metal material that is in the individual openings. The metal material is removed back to have an…