Forming a self-aligned TSV with narrow opening in horizontal isolation layer interfacing substrate
US11482474B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2020 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Apr 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method of manufacturing thereof are provided. The semiconductor device includes a substrate, a first dielectric layer, an isolation layer, a conductor and a liner layer. The substrate has a top surface and a bottom surface opposite the top surface. The first dielectric layer is on the bottom surface of the substrate, in which the first dielectric layer comprises an interconnect structure disposed therein. The isolation layer is on the top surface of the substrate. The conductor is disposed in the substrate and covers a portion of the isolation layer, in which the conductor includes a first portion connected to the interconnect structure and a second portion on the first portion, in which the first portion has a width greater than a width of the second portion. The liner layer is disposed between the substrate and the conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.