Apparatus and methods for plug fill deposition in 3-D NAND applications
US11482533B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Feb 12, 2020 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Feb 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method for forming a 3-D NAND device are disclosed. The method of forming the 3-D NAND device may include forming a plug fill and a void. Advantages gained by the apparatus and method may include a lower cost, a higher throughput, little to no contamination of the device, little to no damage during etching steps, and structural integrity to ensure formation of a proper stack of oxide-nitride bilayers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.