Wafer-to-wafer interconnection structure and method of manufacturing the same
US11488840B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 11, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Apr 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06544
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a wafer-to-wafer interconnection structure includes forming a first etching stop layer with at least two portions on a first surface of a first substrate, and forming a void in one portion of the first etching stop layer. A second etching stop layer is formed on a first surface of a second substrate, and then the first surfaces of the first substrate and the second substrate are bonded, wherein the second etching stop layer is aligned to the void. By using the first and the second etching stop layers as etching stop layers, a first opening is formed from a second surface of the first substrate into the first substrate, and a second opening is formed through the void to the second substrate. A first TSV (through silicon via) is formed in the first opening, and a second TSV is formed in the second opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.