Self-aligned supervia and metal direct etching process to manufacture self-aligned supervia
US11488864B2 · kind B2 · utility
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5References
16Claims
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Key dates
| Filing date | Jan 15, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Feb 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device structure includes: at least one inter-metal layer stacked in a vertical direction; and a 1st via structure penetrating the at least one inter-metal layer, wherein, in the at least one inter-metal layer, a 1st vertical side of the 1st via structure does not contact a barrier metal pattern while a 2nd vertical side of the 1st via structure opposite to the 1st vertical side of the 1st via structure contacts the barrier metal pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.