Thermal enablement of dies with impurity gettering

US11488887B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Gamal Refai-Ahmed · Markham, CA
• Suresh Ramalingam · Fremont, US
• Boon Yong Ang · Cupertino, US
• Toshiyuki Hisamura · San Jose, US
• Suresh Parameswaran · Fremont, US
• Scott McCann · Sunnyvale, US
• Hoa Do · San Jose, US

Key dates

• Filing date: Mar 5, 2020
• Grant date: Nov 1, 2022
• Expiry date: May 12, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In one example, a method includes providing a first side of a semiconductor substrate with a plurality of transistors, etching a second side of the substrate, opposite the first side, with a pattern of trenches, the trenches having a pre-defined depth and width, and providing the etched semiconductor substrate in a package. In one example, the predefined depth and width of the trenches is such so as to increase the surface area of the second side of the substrate by at least 20 percent. In one example, the method also includes providing a layer of a thermal interface material (TIM) on the second side of the substrate, including to fill at least a portion of the trenches.