Read threshold adjustment techniques for non-binary memory cells
US11494114B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2021 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Apr 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for read threshold adjustment techniques for error recovery are described. A memory system may read a codeword from a memory array using one or more read thresholds. The memory system may increment one or more counters of the memory device based on reading the codeword. The one or more counters may indicate information related to how many bits of the codeword correspond to a particular logic value. The memory system may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory system may adjust the one or more read thresholds based on the information indicated by the one or more counters and read the codeword using the adjusted read thresholds.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.