Increased transistor source/drain contact area using sacrificial source/drain layer

US11495672B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Dax M. Crum · Beaverton, US
• Biswajeet Guha · Hillsboro, US
• William Hsu · Hillsboro, US
• Stephen M. Cea · Hillsboro, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Jun 29, 2018
• Grant date: Nov 8, 2022
• Expiry date: Jan 29, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/832
• WIPO field: Micro-structural and nano-technology
• WIPO sector: Chemistry

Abstract

Integrated circuit structures including increased transistor source/drain (S/D) contact area using a sacrificial S/D layer are provided herein. The sacrificial layer, which includes different material from the S/D material, is deposited into the S/D trenches prior to the epitaxial growth of that S/D material, such that the sacrificial layer acts as a space-holder below the S/D material. During S/D contact processing, the sacrificial layer can be selectively etched relative to the S/D material to at least partially remove it, leaving space below the S/D material for the contact metal to fill. In some cases, the contact metal is also between portions of the S/D material. In some cases, the contact metal wraps around the epi S/D, such as when dielectric wall structures on either side of the S/D region are employed. By increasing the S/D contact area, the contact resistance is reduced, thereby improving the performance of the transistor device.