Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed material
US11495683B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2020 |
| Grant date | Nov 8, 2022 |
| Priority date | — |
| Expiry date | Aug 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Multiple strain states in epitaxial transistor channel material may be achieved through the incorporation of stress-relief defects within a seed material. Selective application of strain may improve channel mobility of one carrier type without hindering channel mobility of the other carrier type. A transistor structure may have a heteroepitaxial fin including a first layer of crystalline material directly on a second layer of crystalline material. Within the second layer, a number of defected regions of a threshold minimum dimension are present, which induces the first layer of crystalline material to relax into a lower-strain state. The defected regions may be introduced selectively, for example a through a masked impurity implantation, so that the defected regions may be absent in some transistor structures where a higher-strain state in the first layer of crystalline material is desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.