Selective reference voltage calibration in memory subsystem
US11501820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2021 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Feb 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.