Memory cell with a ferroelectric capacitor integrated with a transtor gate
US11502103B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2018 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Feb 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a “FE capacitor”). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.