Embedded memory devices
US11502242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2020 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Mar 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F41/302
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a base structure of an embedded memory device including a bottom electrode contact (BEC) landing pad within a memory area of the embedded memory device and a first metallization level having at least a first conductive line within a logic area of the embedded memory device, a cap layer disposed on the base structure, a BEC disposed through the cap layer on the BEC landing pad, a memory pillar disposed on the BEC and the cap layer, encapsulation layers encapsulating the memory pillar to protect the memory stack, and a second metallization level including a second conductive line surrounding the top electrode, a via disposed on the first conductive line such that the second via is below the top electrode, and a third conductive line disposed on the via to enable the memory pillar to be fitted between the first and second metallization levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.