Low-latency register error correction
US11507453B2 · kind B2 · utility
1Cited by
9References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2020 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Jan 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To implement low-latency register error correction a register may be read as part of an instruction when that instruction is the currently executing instruction in a processor. A correctable error in data produced from reading the register can be detected. In response to detecting the correctable error, the currently executing instruction in the processor can be changed into a register update instruction that is executed to overwrite the data in the register with corrected data. Then, the original (e.g., unchanged) instruction can be rescheduled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.