Method of forming semiconductor device having capped air gaps between buried bit lines and buried gate
US11508614B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 28, 2020 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Oct 28, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/845
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and method of forming the same, the semiconductor device includes plural bit lines, plural conductive patterns, plural conductive pads and a spacer. The bit lines are disposed on a substrate, along a first direction. The conductive patterns are disposed on the substrate, along the first direction, wherein the conductive patterns and the bit lines are alternately arranged in a second direction perpendicular to the first direction. The conductive pads are arranged in an array and disposed over the conductive patterns and the bit lines. The spacer is disposed between the bit lines and the conductive patterns, under the conductive pads, wherein the spacers includes a tri-layered structure having a first layer, a second layer and a third layer, and the second layer includes a plurality of air gaps separated arranged along the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.