Dual metal silicide structures for advanced integrated circuit structure fabrication
US11508626B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2020 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Feb 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.