Semiconductor package and manufacturing method thereof
US11508671B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2020 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Mar 11, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.