Patent · US Active

Polymer resin and compression mold chip scale package

US11508679B2 · kind B2 · utility

0Cited by

5References

15Claims

0Family size

Assignee

SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC · US

Inventors

Yusheng LIN · Phoenix, US
Soon Wei WANG · Seremban, MY
Chee Hiong CHEW · Seremban, MY
Francis J. Carney · Mesa, US

Key dates

Filing date	Oct 12, 2020
Grant date	Nov 22, 2022
Priority date	—
Expiry date	Feb 13, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2224/96
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to one or more sides of the wafer; and applying a compression mold on at least part of a second surface of the wafer and to one or more sides of the wafer, said first and second surfaces opposing each other.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.