Low leakage ESD MOSFET
US11508806B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2021 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Jun 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/371
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOSFET fabricated in a semiconductor substrate, includes: a gate oxide region formed atop the semiconductor substrate; a gate polysilicon region formed on the gate oxide region; a source region of a first doping type formed in the semiconductor substrate and located at a first side of the gate polysilicon region; and a drain region of the first doping type formed in the semiconductor substrate and located at a second side of the gate polysilicon region. The gate polysilicon region has a first sub-region of the first doping type, a second sub-region of the first doping type, and a third sub-region of a second doping type, wherein the first sub-region is laterally adjacent to the source region, the second sub-region is laterally adjacent to the drain region, and the third sub-region is formed laterally between the first and second sub-regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.