Semiconductor memory device

US11515316B2 · kind B2 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventor

• Tzu-Ping Chen · Hengshan, TW

Key dates

• Filing date: Nov 24, 2020
• Grant date: Nov 29, 2022
• Expiry date: Mar 16, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/60

Abstract

A semiconductor memory device includes a select transistor and a floating gate transistor on a substrate. The select transistor includes a select gate, a select gate oxide layer and a drain doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, a source doping region, a first tunnel doping region and a second tunnel doping region under the floating gate, a first tunnel oxide layer on the first tunnel doping region, and a second tunnel oxide layer on the second tunnel doping region. The floating gate oxide layer is disposed between the first tunnel oxide layer and the second tunnel oxide layer. A lightly doped diffusion region surrounds the source doping region and the second tunnel doping region.