3D NAND structures with decreased pitch
US11515324B2 · kind B2 · utility
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2References
17Claims
0Family size
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Key dates
| Filing date | Dec 19, 2019 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | May 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.