Microelectronic transistor source/drain formation using angled etching
US11515402B2 · kind B2 · utility
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6Claims
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Assignee
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Key dates
| Filing date | Mar 30, 2016 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Oct 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present description relates to the fabrication of microelectronic transistor source and/or drain regions using angled etching. In one embodiment, a microelectronic transistor may be formed by using an angled etch to reduce the number masking steps required to form p-type doped regions and n-type doped regions. In further embodiments, angled etching may be used to form asymmetric spacers on opposing sides of a transistor gate, wherein the asymmetric spacers may result in asymmetric source/drain configurations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.