Parity protection in non-volatile memory
US11520491B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2021 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Apr 17, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method that includes writing a plurality of codewords to a plurality of memory blocks of a memory device, where each of the plurality of codewords has a physical codeword index corresponding to a respective memory block in which each codeword is written, and assigning a virtual codeword index to each of the plurality of codewords to provide a plurality of virtual codeword indices, where assigning the virtual codeword index to each of the plurality of codewords is based, at least in part, on a location in a virtual block among a plurality of virtual blocks of memory cells corresponding to the physical codeword index of each codeword among the plurality of codewords.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.