Triggering next state verify in program loop for nonvolatile memory
US11521691B1 · kind B1 · utility
1Cited by
1References
20Claims
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Key dates
| Filing date | Jun 2, 2021 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Jun 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods are described to program memory cells and control bit line discharge schemes during programming based on the data pattern. The memory controller can predict program data pattern based on SLC pulse number and TLC data completion signals and use these signals to adjust when the inhibited bit lines can discharge. Once a TLC program operation have more one data, the memory controller will enable EQVDDSA_PROG to equalize to VDDSA, and then discharge. In SLC program, the memory controller will enable EQVDDSA_PROG only in first program pulse and disable it thereafter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.