Formal gated clock conversion for field programmable gate array (FPGA) synthesis
US11526641B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2021 |
| Grant date | Dec 13, 2022 |
| Priority date | — |
| Expiry date | Aug 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some aspects of this disclosure are directed to implementing formal gated clock conversion for field programmable gate array (FPGA) synthesis. For example, some aspects of this disclosure relate to a method, including receiving network representation of a circuit design, determining a gated clock function corresponding to a target component of the network representation, and constructing an edge function based at least in part on the gated clock function. The method further includes performing a minimization of the edge function, and in response to a determination that the minimization of the edge function comprises a first term and a second term, providing a clock enable signal to the target component based on the first term, and providing a clock signal to the target component based on the second term.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.