Removal of a bottom-most nanowire from a nanowire device stack
US11527613B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 8, 2021 |
| Grant date | Dec 13, 2022 |
| Priority date | — |
| Expiry date | Jan 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus is provided which comprises: a plurality of nanowire transistors stacked vertically, wherein each nanowire transistor of the plurality of nanowire transistors comprises a corresponding nanowire of a plurality of nanowires; and a gate stack, wherein the gate stack fully encircles at least a section of each nanowire of the plurality of nanowires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.