Patent · US Active

Circuitry apportioning of an integrated circuit

US11532353B2 · kind B2 · utility

0Cited by

1References

16Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Mudit Bhargava · Austin, US
Rahul Mathur · Austin, US
Andy Wangkun Chen · Austin, US

Key dates

Filing date	Jan 29, 2021
Grant date	Dec 20, 2022
Priority date	—
Expiry date	Jan 29, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/418
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

According to one implementation of the present disclosure, an integrated circuit comprises a memory macro unit that includes an input/output (I/O) circuit block, where read/write circuitry of the I/O circuit block is apportioned on at least first and second tiers of the memory macro unit. In a particular implementation, read circuitry of the read/write circuitry is arranged on the first tier and write circuitry of the read/write circuitry is arranged on the second tier.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.