Stacked semiconductor dies for semiconductor device assemblies
US11532595B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 2021 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Mar 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with an opening extending therethrough. The assembly can include a stack of semiconductor dies attached to the substrate. The stack includes a first die attached to a front surface of the substrate, where the first die includes a first bond pad aligned with the opening. The stack also includes a second die attached to the first die such that an edge of the second die extends past a corresponding edge of the first die. The second die includes a second bond pad uncovered by the first die and aligned with the opening. A bond wire formed through the opening couples the first and second bond pads with a substrate bond pad on a back surface of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.