Selective gate spacers for semiconductor devices
US11532724B2 · kind B2 · utility
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5References
20Claims
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Assignee
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Key dates
| Filing date | Jan 21, 2021 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Mar 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques related to forming selective gate spacers for semiconductor devices and transistor structures and devices formed using such techniques are discussed. Such techniques include forming a blocking material on a semiconductor fin, disposing a gate having a different surface chemistry than the blocking material on a portion of the blocking material, forming a selective conformal layer on the gate but not on a portion of the blocking material, and removing exposed portions of the blocking material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.