Memory, memory system, and operation method of memory
US11537467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Jun 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory which includes a downlink error correction circuit suitable for correcting an error in data transferred from a memory controller based on a downlink error correction code transferred from the memory controller to produce an error-corrected data so that when an uncorrectable error is detected in the downlink error correction circuit of the memory or when an uncorrectable error is detected in the memory error correction circuit of the memory, the information that there is an uncorrectable error may be transferred to the memory controller in the memory system by using an uncorrectable error signal and an error flag signal, thus, improving the reliability of the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.