Marking in-flight requests affected by translation entry invalidation in a data processing system
US11537519B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Jul 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory-referent instruction is executed to calculate a target effective address (EA) of a corresponding memory-referent request. An array entry in an upper level cache is allocated, and the EA is specified in a corresponding EA directory entry. While in-flight, the memory-referent request is buffered in a queue in association with a pointer to the entry in the EA directory. Based on receiving a translation invalidation request requesting invalidation of an address translation in a translation structure, the processor core walks the EA directory, determines the EA in the entry matches an address range specified by the translation invalidation request, and, based on the match, precisely marks the memory-referent request using the pointer to the EA directory entry. Based on the marking, the translation invalidation request is permitted to complete with reference to the processor core only after the memory-referent request has drained from the processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.