Semiconductor package and method of fabricating the same
US11538792B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Jan 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.