Transistors and arrays of elevationally-extending strings of memory cells
US11538919B2 · kind B2 · utility
0Cited by
29References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 23, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Feb 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlxFy, HfAlxFy, AlOxNy, and HfAlxOyNz, where “x”, “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.