Bit width reconfiguration using a shadow-latch configured register file
US11544065B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2019 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Sep 27, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30189
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a front-end with an instruction set that operates at a first bit width and a floating point unit coupled to receive the instruction set in the processor that operates at the first bit width. The floating point unit operates at a second bit width and, based upon a bit width assessment of the instruction set provided to the floating point unit, the floating point unit employs a shadow-latch configured floating point register file to perform bit width reconfiguration. The shadow-latch configured floating point register file includes a plurality of regular latches and a plurality of shadow latches for storing data that is to be either read from or written to the shadow latches. The bit width reconfiguration enables the floating point unit that operates at the second bit width to operate on the instruction set received at the first bit width.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.