Memory device with dynamic storage mode control
US11544188B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Mar 9, 2021 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Mar 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory circuits including dynamically configurable cache cells are disclosed herein. The cache cells may be selectively and dynamically configured to select one or more bits per cell according to a real-time determination or characterization of a workload type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.