Hardware-software interaction testing using formal verification
US11544436B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2021 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Jun 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware-software interaction testing is performed using formal verification for language-specified hardware designs. A description of valid access using an interface for a configuration space of a language specified hardware design and a description of a valid output of the language-specified hardware design is received. Formal verification is performed on the language-specified hardware design using the interface for the configuration space according to the description of valid access using the interface. A sequence of access to the configuration space using the interface that causes a failure to produce the valid output of the language-specified hardware design according to the description of valid output to identify as an error for the language-specified hardware design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.