Memory device with single transistor drivers and methods to operate the memory device
US11545219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2020 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Mar 24, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.