Package including multiple semiconductor devices
US11545421B2 · kind B2 · utility
0Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2021 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Jan 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.