Ferroelectric field effect transistors having enhanced memory window and methods of making the same
US11545506B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Nov 13, 2020 |
| Grant date | Jan 3, 2023 |
| Priority date | — |
| Expiry date | Nov 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B51/50
Abstract
A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.