Process of forming an electronic device including a non-volatile memory cell

US11545583B2 · kind B2 · utility

Assignee

• SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC · US

Inventors

• Weize Chen · Phoenix, US
• Sameer Haddad · San Jose, US
• Bruce Greenwood · Gresham, US
• Mark Griswold · Chandler, US
• Kenneth A. Bates · Happy Valley, US

Key dates

• Filing date: Feb 5, 2021
• Grant date: Jan 3, 2023
• Expiry date: Feb 5, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/663

Abstract

An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.