Sameer Haddad
119Patents
25h-index
103Co-inventors
93Inventor score
Filing activity: Jun 17, 1986 → Feb 5, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5077691A | Flash EEPROM array with negative gate voltage erase operation | Physics | 246 | Expired |
| US5712815A | Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells | Physics | 222 | Expired |
| US5335198A | Flash EEPROM array with high endurance | Physics | 157 | Expired |
| US6269023A | Method of programming a non-volatile memory cell using a current limiter | Physics | 139 | Expired |
| US5491657A | Method for bulk (or byte) charging and discharging an array of flash EEPROM memory cells | Physics | 101 | Expired |
| US5617357A | Flash EEPROM memory with improved discharge speed using substrate bias and method therefor | Emerging Cross-Sectional Technologies | 79 | Expired |
| US4774197A | Method of improving silicon dioxide | Emerging Cross-Sectional Technologies | 68 | Expired |
| US6252803A | Automatic program disturb with intelligent soft programming for flash cells | Physics | 66 | Expired |
| US6122198A | Bit by bit APDE verify for flash memory applications | Physics | 45 | Expired |
| US6001713A | Methods for forming nitrogen-rich regions in a floating gate and interpoly dielectric layer in a non-volatile semiconductor memory device | Electricity | 42 | Expired |
| US6240016A | Method to reduce read gate disturb for flash EEPROM application | Physics | 40 | Expired |
| US6456531B1 | Method of drain avalanche programming of a non-volatile memory cell | Physics | 40 | Expired |
| US6172909A | Ramped gate technique for soft programming to tighten the Vt distribution | Physics | 38 | Expired |
| US5457336A | Non-volatile memory structure including protection and structure for maintaining threshold stability | Electricity | 38 | Expired |
| US5793677A | Using floating gate devices as select gate devices for NAND flash memory and its bias scheme | Physics | 38 | Expired |
| US6735114B1 | Method of improving dynamic reference tracking for flash memory unit | Physics | 37 | Expired |
| US6438037B1 | Threshold voltage compacting for non-volatile semiconductor memory designs | Physics | 36 | Expired |
| US7289351B1 | Method of programming a resistive memory device | Physics | 33 | Expired |
| US6275415A | Multiple byte channel hot electron programming using ramped gate and source bias voltage | Physics | 32 | Expired |
| US6583009B1 | Innovative narrow gate formation for floating gate flash technology | Emerging Cross-Sectional Technologies | 31 | Expired |
| US5790456A | Multiple bits-per-cell flash EEPROM memory cells with wide program and erase V.sub.t window | Physics | 29 | Expired |
| US5590076A | Channel hot-carrier page write | Physics | 28 | Expired |
| US6046932A | Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM | Physics | 26 | Expired |
| US5912489A | Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory | Physics | 26 | Expired |
| US5856946A | Memory cell programming with controlled current injection | Physics | 26 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.