Unified hypercall interface across processors in virtualized computing systems
US11550609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2020 |
| Grant date | Jan 10, 2023 |
| Priority date | — |
| Expiry date | Jan 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45579
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example method of interfacing with a hypervisor in a computing system is described, which includes a processor having at least three hierarchical privilege levels including a third privilege level more privileged than a second privilege level, the second privilege level more privileged than a first privilege level. The method includes: identifying an input/output (I/O) space instruction, not supported by the processor, to be performed for backdoor communication between the hypervisor and guest software executing in a virtual machine (VM) managed by the hypervisor, the hypervisor executing at the third privilege level; writing one or more parameters to one or more registers of the processor that are mapped to one or more unsupported registers used by the I/O space instruction; writing a value indicative of the I/O space instruction to a designated register of the processor; executing an instruction, by the guest software executing at the first or second privilege level, which is trapped to the third privilege level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.