Patent · US Active

Sense circuit to sense two states of a memory cell

US11557351B2 · kind B2 · utility

0Cited by

0References

20Claims

0Family size

Assignee

Micron Technology, Inc. · US

Inventors

Luyen Vu · San Jose, US
Erwin E. Yu · San Jose, US
Jeffrey Ming-Hung Tsai · Torrance, US

Key dates

Filing date	Apr 19, 2021
Grant date	Jan 17, 2023
Priority date	—
Expiry date	Jul 15, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/5671
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A device includes a memory array and a sense circuit coupled with the memory array. The sense circuit includes a sense node coupled with a data line of the memory array. A first sensing path includes a first transistor having a first gate coupled with the sense node. A second sensing path includes a second transistor having a second gate coupled with the sense node. A first threshold voltage of the first transistors differs from a second threshold voltage of the second transistor by a threshold voltage gap.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.