Patent · US Active

Cell architecture

US11557583B2 · kind B2 · utility

2Cited by

2References

20Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Andy Wangkun Chen · Austin, US
Sriram Thyagarajan · Austin, US
Yew Keong Chong · Austin, US
Sony · Noida, IN

Key dates

Filing date	Sep 10, 2020
Grant date	Jan 17, 2023
Priority date	—
Expiry date	Jul 20, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/85
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein refer to a device having logic circuitry with transistors and gate lines. The device may include a backside power network having buried supply rails with at least one buried supply rail having a continuity break. The transistors may be arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.