Bit line secondary drive circuit and method
US11562779B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2020 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Dec 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a reference node configured to carry a reference voltage having a reference voltage level, a power supply node configured to carry a power supply voltage having a power supply voltage level, a bit line coupled with a plurality of memory cells, a write circuit configured to charge the bit line by driving a voltage level on the bit line toward the power supply voltage level with a first current, and a switching circuit coupled between the power supply node and the bit line. The switching circuit is configured to receive the voltage level on the bit line, and responsive to a difference between the voltage level received on the bit line and the power supply voltage level being less than or equal to a threshold value, drive the voltage level on the bit line toward the power supply voltage level with a second current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.