Memory devices with low pin count interfaces, and corresponding methods and systems
US11562781B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2021 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Oct 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method can include, in an integrated circuit device: at a unidirectional command-address (CA) bus having no more than four parallel inputs, receiving a sequence of no less than three command value portions; latching each command value portion in synchronism with rising edges of a timing clock; determining an input command from the sequence of no less than three command value portions; executing the input command in the integrated circuit device; and on a bi-directional data bus having no more than six data input/outputs (IOs), outputting and inputting sequences of data values in synchronism with rising and falling edges of the timing clock. Corresponding devices and systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.