Integrated circuitry, memory circuitry, method used in forming integrated circuitry, and method used in forming memory circuitry
US11563011B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Jan 24, 2023 |
| Priority date | — |
| Expiry date | Feb 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.