Method of contact patterning of thin film transistors for embedded DRAM using a multi-layer hardmask

US11563107B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Chieh-Jen Ku · Hillsboro, US
• Bernhard Sell · Dresden, DE
• Pei-Hua Wang · Beaverton, US
• Nikhil MEHTA · Portland, US
• Shu Zhou · Portland, US
• Jared Stoeger · Portland, US
• Allen B. Gardiner · Portland, US
• Akash Garg · Portland, US
• Shem Ogadhoh · Beaverton, US
• Vinaykumar Hadagali · Portland, US
• Travis W. Lajoie · Forest Grove, US

Key dates

• Filing date: Mar 22, 2019
• Grant date: Jan 24, 2023
• Expiry date: May 25, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/60
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).